Although applicable in principle to arbitrary bipolar transistors, the present invention and the problem area on which it is based will be explained with regard to DPSA transistors.
DPSA (double polysilicon self-aligned) transistors, as disclosed e.g. in T. F. Meister et al., IEDM Technical Digest 1995, pp. 739–741, use, as p+-type base terminal and as n+-type emitter contact, p+-type polysilicon and respectively n+-type polysilicon layers that are especially deposited therefor. In this case, in the emitter window, the n+-type polysilicon emitter layer is insulated from the p+-type polysilicon layer of the base terminal by a spacer in a self-aligned manner. On account of its lateral and vertical scalability and the small parasitic capacitance and resistance components, the DPSA transistor structure is best suited to very high speed applications. In this case, the DPSA transistor may contain both an implanted Si base and an epitaxially deposited SiGe base.
FIG. 4 is a schematic illustration of a known DPSA transistor as disclosed in T. F. Meister et al., IEDM Technical Digest 1995, pp. 739–741.
In FIG. 4, reference symbol 1 designates a silicon semiconductor substrate, 10 designates an n+-type subcollector region in the form of a buried layer, 20 designates p+-type channel blocking regions, 25 designates an n−-type collector region, 30 designates a p-type base region, 35 designates a CVD insulation oxide layer, 15 designates a LOCOS insulation oxide layer, 40 designates a p+-type base terminal, 45 designates an n+-type collector contact, 55 designates a double spacer comprising silicon oxide/silicon nitride, and 50 designates an n+-type emitter contact.
FIGS. 5a–c are schematic illustrations of the method steps with regard to the emitter contact of a customary method for the production of a DPSA transistor, in contrast to FIG. 1 reference symbol 55′ designating a single spacer made of oxide. Reference symbol F designates the emitter window in the layers 35 and 40.
In order to produce the n+-type emitter contact, in the case of the DPSA transistor, after the formation of the oxide spacer 55′ covering the sidewalls of the emitter window F, on the active p+-type base region, an n+-doped (implanted or in situ doped) n+-type polysilicon layer 60 is applied in polycrystalline fashion on the active transistor zone and also on the surrounding insulation regions.
Afterward, the n+-type polysilicon layer 60 is patterned anisotropically by means of a phototechnology for the purpose of forming the final emitter contact 60 and the n+-type dopant is driven e.g. 20 nm into the underlying monocrystalline Si material of the base region 30 by means of a thermal step (FIG. 5c). This gives rise to an n+-type emitter composed of a monocrystalline portion 31 and a polycrystalline portion 50.
In this production method, a natural oxide film 36 of 0.5–2 nm forms in the time between spacer etching and n+-type polysilicon emitter deposition on the active transistor zone between the monocrystalline and polycrystalline parts of the emitter. The thickness of said natural oxide layer 36, which can be controlled only with extreme difficulty, influences both the current gain appreciably and the emitter resistance of the DPSA transistor.
In the case of DPSA transistors having an implanted Si base, the natural interface oxide 36 was necessary in order to achieve a sufficiently high current gain. By contrast, in the case of an integrated SiGe base, the natural oxide layer 36 is no longer necessary since such DPSA transistors already achieve sufficiently high current gains solely on account of the Ge content in the base. Moreover, with increasing lateral scaling of the emitter window F in these DPSA transistors, the rise in the emitter resistance becomes apparent in a disadvantageous manner to an ever greater extent. This is because this rise in the emitter resistance leads to a significant reduction in the limiting frequency and nowadays limits the lateral scalability of the DPSA transistor.
This is caused by said natural interface oxide 36 in the poly/mono intermediate layer of the n+-type emitter and also the limited conductivity of the n+-type polysilicon layer in the narrow emitter window F of the DPSA transistor.
On the other hand, SiGe bipolar transistor structures that deviate from the DPSA transistor are known, in the case of which the integrated n+-type emitter is entirely monocrystalline (see H. U. Schreiber et al., Electronic Letters 1989, Vol. 25, pp. 185–186).
Thus, in accordance with H. U. Schreiber et al., loc. cit., a so-called double mesa transistor is described, for the production of which firstly the n−-doped collector, the SiGe base, an n−-doped epitaxial emitter and an n+-doped monocrystalline emitter cap are applied on a bare Si wafer in a single epitaxy step. Afterward, the applied epitaxial layers are patterned and suitably contact-connected by means of a metallization. In comparison with the DPSA transistor, the double mesa transistor has significantly larger lateral dimensions that limit the circuit performance of this transistor structure. Thus, by way of example, in this transistor structure, the lateral, effective emitter width must always be larger than the contact hole that makes contact with the emitter.
Equally, in accordance with U.S. Pat. No. 6,177,717 B1 a single-poly (SP) transistor is described, in which the n+-doped emitter region is deposited onto the SiGe base in monocrystalline fashion in a CVD reactor. Such SP transistors also have significant disadvantages in comparison with the DPSA transistor structure. By way of example, the additional p+-type polysilicon deposition (thickness approximately 100–200 nm) is absent, this deposition being carried out in the case of the DPSA transistor for the purpose of reducing the base contact resistance. Therefore, although the SP transistor has a more planar topology in the emitter window, it also requires a p+-type implantation into the monocrystalline SiGe base terminal zone after the SiGe base deposition in order to improve the base bulk resistance. Said p+-type implantation produces point defects which, during the subsequent process steps, diffuse into the nearby active base, where they lead to a significant widening of the vertical base profile and thus to a significant reduction of the limiting frequency. In this planar transistor structure, the n+-type emitter deposited in monocrystalline fashion (in comparison with the n+-type poly/mono emitter) was introduced in order to improve the low-frequency noise.
It is an object of the invention to specify an improved method for the production of a bipolar transistor, in which case the emitter resistance can be kept as low as possible.
This object is achieved by means of a method of a bipolar transistor according to claim 1.
The present invention provides a production method for a bipolar transistor in which both the poly/mono Si boundary layer and the natural oxide film contained therein are no longer present, so that it is possible to produce transistors with the smallest possible emitter resistance.
The subclaims relate to preferred developments.
In accordance with one preferred development, carbon is incorporated into the emitter layer. A later outdiffusion of the base layer can thus be prevented.
In accordance with a further preferred development, the heat treatment step is a rapid annealing step, preferably a lamp annealing step.
In accordance with a further preferred development, a second insulation region is provided between the collector region and the base terminal region, and is opened by means of a wet-chemical etching in the window before the base region is formed selectively in the emitter window on the collector region.
In accordance with a further preferred development, the base region is deposited over the whole area of the semiconductor substrate with a collector region embedded therein, said collector region being bare toward the top, a mask region is formed above the base region in accordance with the later emitter window, said mask region being embedded in the base terminal region and the overlying first insulation region, after which the window is formed.
In accordance with a further preferred development, the base terminal region is grown above the base region by means of selective epitaxy in a manner doped in situ.
In accordance with a further preferred development, the mask region has an oxide layer and an overlying nitride layer, the nitride layer is removed during the formation of the window, the first sidewall spacer is formed in the window on the oxide layer, and then the oxide layer is opened by means of a wet-chemical etching.
In accordance with a further preferred development, the base region has a lower, more highly doped first base foundation layer and an upper, more lightly doped base cap layer, above which the base terminal region is provided, the base cap layer being doped upward during the heat treatment step from the base terminal region.
In accordance with a further preferred development, the base cap layer is thinned after the formation of the mask region. This ensures reliable upward doping.
In accordance with a further preferred development, the removal of the natural oxide in the uncovered base region takes place in an epitaxy reactor by means of a heat treatment in a hydrogen atmosphere and the differential deposition of the emitter layer is subsequently carried out in situ in the epitaxy reactor.
The invention is explained in more detail below on the basis of exemplary embodiments with reference to the drawings.